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- // ==============================================================
- // RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and OpenCL
- // Version: 2019.2
- // Copyright (C) 1986-2019 Xilinx, Inc. All Rights Reserved.
- //
- // ===========================================================
-
- `timescale 1 ns / 1 ps
-
- module select_ipm (
- ap_clk,
- ap_rst,
- ap_start,
- ap_done,
- ap_idle,
- ap_ready,
- nb0_0_address0,
- nb0_0_ce0,
- nb0_0_q0,
- nb0_1_address0,
- nb0_1_ce0,
- nb0_1_q0,
- nb1_address0,
- nb1_ce0,
- nb1_q0,
- nb1_address1,
- nb1_ce1,
- nb1_q1,
- nb2_address0,
- nb2_ce0,
- nb2_q0,
- nb2_address1,
- nb2_ce1,
- nb2_q1,
- nb3le_address0,
- nb3le_ce0,
- nb3le_q0,
- nb3up_address0,
- nb3up_ce0,
- nb3up_q0,
- nb3up_address1,
- nb3up_ce1,
- nb3up_q1,
- nb4_address0,
- nb4_ce0,
- nb4_q0,
- nb4_address1,
- nb4_ce1,
- nb4_q1,
- nb5_address0,
- nb5_ce0,
- nb5_q0,
- nb5_address1,
- nb5_ce1,
- nb5_q1,
- dst0_address0,
- dst0_ce0,
- dst0_we0,
- dst0_d0,
- dst0_address1,
- dst0_ce1,
- dst0_we1,
- dst0_d1,
- dst1_address0,
- dst1_ce0,
- dst1_we0,
- dst1_d0,
- dst2_address0,
- dst2_ce0,
- dst2_we0,
- dst2_d0,
- dst3_address0,
- dst3_ce0,
- dst3_we0,
- dst3_d0,
- dst4_address0,
- dst4_ce0,
- dst4_we0,
- dst4_d0,
- dst5_address0,
- dst5_ce0,
- dst5_we0,
- dst5_d0,
- resi0_0_address0,
- resi0_0_ce0,
- resi0_0_we0,
- resi0_0_d0,
- resi0_1_address0,
- resi0_1_ce0,
- resi0_1_we0,
- resi0_1_d0,
- resi1_0_address0,
- resi1_0_ce0,
- resi1_0_we0,
- resi1_0_d0,
- resi1_1_address0,
- resi1_1_ce0,
- resi1_1_we0,
- resi1_1_d0,
- resi2_0_address0,
- resi2_0_ce0,
- resi2_0_we0,
- resi2_0_d0,
- resi2_1_address0,
- resi2_1_ce0,
- resi2_1_we0,
- resi2_1_d0,
- resi3_0_address0,
- resi3_0_ce0,
- resi3_0_we0,
- resi3_0_d0,
- resi3_1_address0,
- resi3_1_ce0,
- resi3_1_we0,
- resi3_1_d0,
- resi4_0_address0,
- resi4_0_ce0,
- resi4_0_we0,
- resi4_0_d0,
- resi4_1_address0,
- resi4_1_ce0,
- resi4_1_we0,
- resi4_1_d0,
- resi5_0_address0,
- resi5_0_ce0,
- resi5_0_we0,
- resi5_0_d0,
- resi5_1_address0,
- resi5_1_ce0,
- resi5_1_we0,
- resi5_1_d0,
- cost_0_read,
- cost_1_read,
- cost_2_read,
- cost_3_read,
- cost_4_read,
- cost_5_read,
- ipm_ang,
- cu_w,
- cu_h,
- cu_org0_0_address0,
- cu_org0_0_ce0,
- cu_org0_0_q0,
- cu_org0_1_address0,
- cu_org0_1_ce0,
- cu_org0_1_q0,
- cu_org1_0_address0,
- cu_org1_0_ce0,
- cu_org1_0_q0,
- cu_org1_1_address0,
- cu_org1_1_ce0,
- cu_org1_1_q0,
- cu_org2_0_address0,
- cu_org2_0_ce0,
- cu_org2_0_q0,
- cu_org2_1_address0,
- cu_org2_1_ce0,
- cu_org2_1_q0,
- cu_org3_1_address0,
- cu_org3_1_ce0,
- cu_org3_1_q0,
- cu_org3_0_address0,
- cu_org3_0_ce0,
- cu_org3_0_q0,
- cu_org4_1_address0,
- cu_org4_1_ce0,
- cu_org4_1_q0,
- cu_org4_0_address0,
- cu_org4_0_ce0,
- cu_org4_0_q0,
- cu_org5_0_address0,
- cu_org5_0_ce0,
- cu_org5_0_q0,
- cu_org5_1_address0,
- cu_org5_1_ce0,
- cu_org5_1_q0,
- ap_return_0,
- ap_return_1,
- ap_return_2,
- ap_return_3,
- ap_return_4,
- ap_return_5
- );
-
- parameter ap_ST_fsm_state1 = 3'd1;
- parameter ap_ST_fsm_state2 = 3'd2;
- parameter ap_ST_fsm_state3 = 3'd4;
-
- input ap_clk;
- input ap_rst;
- input ap_start;
- output ap_done;
- output ap_idle;
- output ap_ready;
- output [7:0] nb0_0_address0;
- output nb0_0_ce0;
- input [9:0] nb0_0_q0;
- output [7:0] nb0_1_address0;
- output nb0_1_ce0;
- input [9:0] nb0_1_q0;
- output [8:0] nb1_address0;
- output nb1_ce0;
- input [9:0] nb1_q0;
- output [8:0] nb1_address1;
- output nb1_ce1;
- input [9:0] nb1_q1;
- output [8:0] nb2_address0;
- output nb2_ce0;
- input [9:0] nb2_q0;
- output [8:0] nb2_address1;
- output nb2_ce1;
- input [9:0] nb2_q1;
- output [7:0] nb3le_address0;
- output nb3le_ce0;
- input [9:0] nb3le_q0;
- output [7:0] nb3up_address0;
- output nb3up_ce0;
- input [9:0] nb3up_q0;
- output [7:0] nb3up_address1;
- output nb3up_ce1;
- input [9:0] nb3up_q1;
- output [8:0] nb4_address0;
- output nb4_ce0;
- input [9:0] nb4_q0;
- output [8:0] nb4_address1;
- output nb4_ce1;
- input [9:0] nb4_q1;
- output [8:0] nb5_address0;
- output nb5_ce0;
- input [9:0] nb5_q0;
- output [8:0] nb5_address1;
- output nb5_ce1;
- input [9:0] nb5_q1;
- output [11:0] dst0_address0;
- output dst0_ce0;
- output dst0_we0;
- output [9:0] dst0_d0;
- output [11:0] dst0_address1;
- output dst0_ce1;
- output dst0_we1;
- output [9:0] dst0_d1;
- output [11:0] dst1_address0;
- output dst1_ce0;
- output dst1_we0;
- output [9:0] dst1_d0;
- output [11:0] dst2_address0;
- output dst2_ce0;
- output dst2_we0;
- output [9:0] dst2_d0;
- output [11:0] dst3_address0;
- output dst3_ce0;
- output dst3_we0;
- output [9:0] dst3_d0;
- output [11:0] dst4_address0;
- output dst4_ce0;
- output dst4_we0;
- output [9:0] dst4_d0;
- output [11:0] dst5_address0;
- output dst5_ce0;
- output dst5_we0;
- output [9:0] dst5_d0;
- output [10:0] resi0_0_address0;
- output resi0_0_ce0;
- output resi0_0_we0;
- output [10:0] resi0_0_d0;
- output [10:0] resi0_1_address0;
- output resi0_1_ce0;
- output resi0_1_we0;
- output [10:0] resi0_1_d0;
- output [10:0] resi1_0_address0;
- output resi1_0_ce0;
- output resi1_0_we0;
- output [10:0] resi1_0_d0;
- output [10:0] resi1_1_address0;
- output resi1_1_ce0;
- output resi1_1_we0;
- output [10:0] resi1_1_d0;
- output [10:0] resi2_0_address0;
- output resi2_0_ce0;
- output resi2_0_we0;
- output [10:0] resi2_0_d0;
- output [10:0] resi2_1_address0;
- output resi2_1_ce0;
- output resi2_1_we0;
- output [10:0] resi2_1_d0;
- output [10:0] resi3_0_address0;
- output resi3_0_ce0;
- output resi3_0_we0;
- output [10:0] resi3_0_d0;
- output [10:0] resi3_1_address0;
- output resi3_1_ce0;
- output resi3_1_we0;
- output [10:0] resi3_1_d0;
- output [10:0] resi4_0_address0;
- output resi4_0_ce0;
- output resi4_0_we0;
- output [10:0] resi4_0_d0;
- output [10:0] resi4_1_address0;
- output resi4_1_ce0;
- output resi4_1_we0;
- output [10:0] resi4_1_d0;
- output [10:0] resi5_0_address0;
- output resi5_0_ce0;
- output resi5_0_we0;
- output [10:0] resi5_0_d0;
- output [10:0] resi5_1_address0;
- output resi5_1_ce0;
- output resi5_1_we0;
- output [10:0] resi5_1_d0;
- input [23:0] cost_0_read;
- input [23:0] cost_1_read;
- input [23:0] cost_2_read;
- input [23:0] cost_3_read;
- input [23:0] cost_4_read;
- input [23:0] cost_5_read;
- input [6:0] ipm_ang;
- input [6:0] cu_w;
- input [6:0] cu_h;
- output [10:0] cu_org0_0_address0;
- output cu_org0_0_ce0;
- input [9:0] cu_org0_0_q0;
- output [10:0] cu_org0_1_address0;
- output cu_org0_1_ce0;
- input [9:0] cu_org0_1_q0;
- output [10:0] cu_org1_0_address0;
- output cu_org1_0_ce0;
- input [9:0] cu_org1_0_q0;
- output [10:0] cu_org1_1_address0;
- output cu_org1_1_ce0;
- input [9:0] cu_org1_1_q0;
- output [10:0] cu_org2_0_address0;
- output cu_org2_0_ce0;
- input [9:0] cu_org2_0_q0;
- output [10:0] cu_org2_1_address0;
- output cu_org2_1_ce0;
- input [9:0] cu_org2_1_q0;
- output [10:0] cu_org3_1_address0;
- output cu_org3_1_ce0;
- input [9:0] cu_org3_1_q0;
- output [10:0] cu_org3_0_address0;
- output cu_org3_0_ce0;
- input [9:0] cu_org3_0_q0;
- output [10:0] cu_org4_1_address0;
- output cu_org4_1_ce0;
- input [9:0] cu_org4_1_q0;
- output [10:0] cu_org4_0_address0;
- output cu_org4_0_ce0;
- input [9:0] cu_org4_0_q0;
- output [10:0] cu_org5_0_address0;
- output cu_org5_0_ce0;
- input [9:0] cu_org5_0_q0;
- output [10:0] cu_org5_1_address0;
- output cu_org5_1_ce0;
- input [9:0] cu_org5_1_q0;
- output [23:0] ap_return_0;
- output [23:0] ap_return_1;
- output [23:0] ap_return_2;
- output [23:0] ap_return_3;
- output [23:0] ap_return_4;
- output [23:0] ap_return_5;
-
- reg ap_done;
- reg ap_idle;
- reg ap_ready;
-
- (* fsm_encoding = "none" *) reg [2:0] ap_CS_fsm;
- wire ap_CS_fsm_state1;
- wire [2:0] i_fu_606_p2;
- wire ap_CS_fsm_state3;
- wire grp_ipred_dc_fu_257_ap_start;
- wire grp_ipred_dc_fu_257_ap_done;
- wire grp_ipred_dc_fu_257_ap_idle;
- wire grp_ipred_dc_fu_257_ap_ready;
- wire [7:0] grp_ipred_dc_fu_257_src_up_address0;
- wire grp_ipred_dc_fu_257_src_up_ce0;
- wire [7:0] grp_ipred_dc_fu_257_src_up2_address0;
- wire grp_ipred_dc_fu_257_src_up2_ce0;
- wire [11:0] grp_ipred_dc_fu_257_dst_address0;
- wire grp_ipred_dc_fu_257_dst_ce0;
- wire grp_ipred_dc_fu_257_dst_we0;
- wire [9:0] grp_ipred_dc_fu_257_dst_d0;
- wire [11:0] grp_ipred_dc_fu_257_dst_address1;
- wire grp_ipred_dc_fu_257_dst_ce1;
- wire grp_ipred_dc_fu_257_dst_we1;
- wire [9:0] grp_ipred_dc_fu_257_dst_d1;
- wire [10:0] grp_ipred_dc_fu_257_cu_org_0_address0;
- wire grp_ipred_dc_fu_257_cu_org_0_ce0;
- wire [10:0] grp_ipred_dc_fu_257_cu_org_1_address0;
- wire grp_ipred_dc_fu_257_cu_org_1_ce0;
- wire [10:0] grp_ipred_dc_fu_257_resi_0_address0;
- wire grp_ipred_dc_fu_257_resi_0_ce0;
- wire grp_ipred_dc_fu_257_resi_0_we0;
- wire [10:0] grp_ipred_dc_fu_257_resi_0_d0;
- wire [10:0] grp_ipred_dc_fu_257_resi_1_address0;
- wire grp_ipred_dc_fu_257_resi_1_ce0;
- wire grp_ipred_dc_fu_257_resi_1_we0;
- wire [10:0] grp_ipred_dc_fu_257_resi_1_d0;
- wire grp_ipred_plane_fu_307_ap_start;
- wire grp_ipred_plane_fu_307_ap_done;
- wire grp_ipred_plane_fu_307_ap_idle;
- wire grp_ipred_plane_fu_307_ap_ready;
- wire [8:0] grp_ipred_plane_fu_307_src_le_address0;
- wire grp_ipred_plane_fu_307_src_le_ce0;
- wire [8:0] grp_ipred_plane_fu_307_src_le_address1;
- wire grp_ipred_plane_fu_307_src_le_ce1;
- wire [11:0] grp_ipred_plane_fu_307_dst_address0;
- wire grp_ipred_plane_fu_307_dst_ce0;
- wire grp_ipred_plane_fu_307_dst_we0;
- wire [9:0] grp_ipred_plane_fu_307_dst_d0;
- wire [10:0] grp_ipred_plane_fu_307_cu_org_0_address0;
- wire grp_ipred_plane_fu_307_cu_org_0_ce0;
- wire [10:0] grp_ipred_plane_fu_307_cu_org_1_address0;
- wire grp_ipred_plane_fu_307_cu_org_1_ce0;
- wire [10:0] grp_ipred_plane_fu_307_resi_0_address0;
- wire grp_ipred_plane_fu_307_resi_0_ce0;
- wire grp_ipred_plane_fu_307_resi_0_we0;
- wire [10:0] grp_ipred_plane_fu_307_resi_0_d0;
- wire [10:0] grp_ipred_plane_fu_307_resi_1_address0;
- wire grp_ipred_plane_fu_307_resi_1_ce0;
- wire grp_ipred_plane_fu_307_resi_1_we0;
- wire [10:0] grp_ipred_plane_fu_307_resi_1_d0;
- wire grp_ipred_bi_fu_361_ap_start;
- wire grp_ipred_bi_fu_361_ap_done;
- wire grp_ipred_bi_fu_361_ap_idle;
- wire grp_ipred_bi_fu_361_ap_ready;
- wire [8:0] grp_ipred_bi_fu_361_src_le_address0;
- wire grp_ipred_bi_fu_361_src_le_ce0;
- wire [8:0] grp_ipred_bi_fu_361_src_le_address1;
- wire grp_ipred_bi_fu_361_src_le_ce1;
- wire [11:0] grp_ipred_bi_fu_361_dst_address0;
- wire grp_ipred_bi_fu_361_dst_ce0;
- wire grp_ipred_bi_fu_361_dst_we0;
- wire [9:0] grp_ipred_bi_fu_361_dst_d0;
- wire [10:0] grp_ipred_bi_fu_361_cu_org_0_address0;
- wire grp_ipred_bi_fu_361_cu_org_0_ce0;
- wire [10:0] grp_ipred_bi_fu_361_cu_org_1_address0;
- wire grp_ipred_bi_fu_361_cu_org_1_ce0;
- wire [10:0] grp_ipred_bi_fu_361_resi_0_address0;
- wire grp_ipred_bi_fu_361_resi_0_ce0;
- wire grp_ipred_bi_fu_361_resi_0_we0;
- wire [10:0] grp_ipred_bi_fu_361_resi_0_d0;
- wire [10:0] grp_ipred_bi_fu_361_resi_1_address0;
- wire grp_ipred_bi_fu_361_resi_1_ce0;
- wire grp_ipred_bi_fu_361_resi_1_we0;
- wire [10:0] grp_ipred_bi_fu_361_resi_1_d0;
- wire grp_ipred_vert_fu_411_ap_start;
- wire grp_ipred_vert_fu_411_ap_done;
- wire grp_ipred_vert_fu_411_ap_idle;
- wire grp_ipred_vert_fu_411_ap_ready;
- wire [7:0] grp_ipred_vert_fu_411_src_up_address0;
- wire grp_ipred_vert_fu_411_src_up_ce0;
- wire [7:0] grp_ipred_vert_fu_411_src_up_address1;
- wire grp_ipred_vert_fu_411_src_up_ce1;
- wire [11:0] grp_ipred_vert_fu_411_dst_address0;
- wire grp_ipred_vert_fu_411_dst_ce0;
- wire grp_ipred_vert_fu_411_dst_we0;
- wire [9:0] grp_ipred_vert_fu_411_dst_d0;
- wire [10:0] grp_ipred_vert_fu_411_resi_0_address0;
- wire grp_ipred_vert_fu_411_resi_0_ce0;
- wire grp_ipred_vert_fu_411_resi_0_we0;
- wire [10:0] grp_ipred_vert_fu_411_resi_0_d0;
- wire [10:0] grp_ipred_vert_fu_411_resi_1_address0;
- wire grp_ipred_vert_fu_411_resi_1_ce0;
- wire grp_ipred_vert_fu_411_resi_1_we0;
- wire [10:0] grp_ipred_vert_fu_411_resi_1_d0;
- wire [10:0] grp_ipred_vert_fu_411_cu_org3_1_address0;
- wire grp_ipred_vert_fu_411_cu_org3_1_ce0;
- wire [10:0] grp_ipred_vert_fu_411_cu_org3_0_address0;
- wire grp_ipred_vert_fu_411_cu_org3_0_ce0;
- wire grp_ipred_hor_fu_453_ap_start;
- wire grp_ipred_hor_fu_453_ap_done;
- wire grp_ipred_hor_fu_453_ap_idle;
- wire grp_ipred_hor_fu_453_ap_ready;
- wire [7:0] grp_ipred_hor_fu_453_src_le_address0;
- wire grp_ipred_hor_fu_453_src_le_ce0;
- wire [11:0] grp_ipred_hor_fu_453_dst_address0;
- wire grp_ipred_hor_fu_453_dst_ce0;
- wire grp_ipred_hor_fu_453_dst_we0;
- wire [9:0] grp_ipred_hor_fu_453_dst_d0;
- wire [10:0] grp_ipred_hor_fu_453_resi_0_address0;
- wire grp_ipred_hor_fu_453_resi_0_ce0;
- wire grp_ipred_hor_fu_453_resi_0_we0;
- wire [10:0] grp_ipred_hor_fu_453_resi_0_d0;
- wire [10:0] grp_ipred_hor_fu_453_resi_1_address0;
- wire grp_ipred_hor_fu_453_resi_1_ce0;
- wire grp_ipred_hor_fu_453_resi_1_we0;
- wire [10:0] grp_ipred_hor_fu_453_resi_1_d0;
- wire [10:0] grp_ipred_hor_fu_453_cu_org4_1_address0;
- wire grp_ipred_hor_fu_453_cu_org4_1_ce0;
- wire [10:0] grp_ipred_hor_fu_453_cu_org4_0_address0;
- wire grp_ipred_hor_fu_453_cu_org4_0_ce0;
- wire grp_ipred_ang_fu_495_ap_start;
- wire grp_ipred_ang_fu_495_ap_done;
- wire grp_ipred_ang_fu_495_ap_idle;
- wire grp_ipred_ang_fu_495_ap_ready;
- wire [8:0] grp_ipred_ang_fu_495_src_le0_address0;
- wire grp_ipred_ang_fu_495_src_le0_ce0;
- wire [8:0] grp_ipred_ang_fu_495_src_le0_address1;
- wire grp_ipred_ang_fu_495_src_le0_ce1;
- wire [8:0] grp_ipred_ang_fu_495_src_le1_address0;
- wire grp_ipred_ang_fu_495_src_le1_ce0;
- wire [8:0] grp_ipred_ang_fu_495_src_le1_address1;
- wire grp_ipred_ang_fu_495_src_le1_ce1;
- wire [11:0] grp_ipred_ang_fu_495_dst_address0;
- wire grp_ipred_ang_fu_495_dst_ce0;
- wire grp_ipred_ang_fu_495_dst_we0;
- wire [9:0] grp_ipred_ang_fu_495_dst_d0;
- wire [10:0] grp_ipred_ang_fu_495_cu_org_0_address0;
- wire grp_ipred_ang_fu_495_cu_org_0_ce0;
- wire [10:0] grp_ipred_ang_fu_495_cu_org_1_address0;
- wire grp_ipred_ang_fu_495_cu_org_1_ce0;
- wire [10:0] grp_ipred_ang_fu_495_resi_0_address0;
- wire grp_ipred_ang_fu_495_resi_0_ce0;
- wire grp_ipred_ang_fu_495_resi_0_we0;
- wire [10:0] grp_ipred_ang_fu_495_resi_0_d0;
- wire [10:0] grp_ipred_ang_fu_495_resi_1_address0;
- wire grp_ipred_ang_fu_495_resi_1_ce0;
- wire grp_ipred_ang_fu_495_resi_1_we0;
- wire [10:0] grp_ipred_ang_fu_495_resi_1_d0;
- wire [2:0] ap_phi_mux_i_0_phi_fu_250_p4;
- reg [2:0] i_0_reg_246;
- wire ap_CS_fsm_state2;
- reg ap_block_state2_on_subcall_done;
- wire [0:0] icmp_ln2106_fu_600_p2;
- reg grp_ipred_dc_fu_257_ap_start_reg;
- reg grp_ipred_plane_fu_307_ap_start_reg;
- reg grp_ipred_bi_fu_361_ap_start_reg;
- reg grp_ipred_vert_fu_411_ap_start_reg;
- reg grp_ipred_hor_fu_453_ap_start_reg;
- reg grp_ipred_ang_fu_495_ap_start_reg;
- reg [23:0] cost18_0_fu_168;
- reg [23:0] cost17_0_fu_172;
- reg [23:0] cost16_0_fu_176;
- reg [23:0] cost15_0_fu_180;
- reg [23:0] cost14_0_fu_184;
- reg [23:0] cost_0_fu_188;
- reg [2:0] ap_NS_fsm;
-
- // power-on initialization
- initial begin
- #0 ap_CS_fsm = 3'd1;
- #0 grp_ipred_dc_fu_257_ap_start_reg = 1'b0;
- #0 grp_ipred_plane_fu_307_ap_start_reg = 1'b0;
- #0 grp_ipred_bi_fu_361_ap_start_reg = 1'b0;
- #0 grp_ipred_vert_fu_411_ap_start_reg = 1'b0;
- #0 grp_ipred_hor_fu_453_ap_start_reg = 1'b0;
- #0 grp_ipred_ang_fu_495_ap_start_reg = 1'b0;
- end
-
- ipred_dc grp_ipred_dc_fu_257(
- .ap_clk(ap_clk),
- .ap_rst(ap_rst),
- .ap_start(grp_ipred_dc_fu_257_ap_start),
- .ap_done(grp_ipred_dc_fu_257_ap_done),
- .ap_idle(grp_ipred_dc_fu_257_ap_idle),
- .ap_ready(grp_ipred_dc_fu_257_ap_ready),
- .src_up_address0(grp_ipred_dc_fu_257_src_up_address0),
- .src_up_ce0(grp_ipred_dc_fu_257_src_up_ce0),
- .src_up_q0(nb0_0_q0),
- .src_up2_address0(grp_ipred_dc_fu_257_src_up2_address0),
- .src_up2_ce0(grp_ipred_dc_fu_257_src_up2_ce0),
- .src_up2_q0(nb0_1_q0),
- .dst_address0(grp_ipred_dc_fu_257_dst_address0),
- .dst_ce0(grp_ipred_dc_fu_257_dst_ce0),
- .dst_we0(grp_ipred_dc_fu_257_dst_we0),
- .dst_d0(grp_ipred_dc_fu_257_dst_d0),
- .dst_address1(grp_ipred_dc_fu_257_dst_address1),
- .dst_ce1(grp_ipred_dc_fu_257_dst_ce1),
- .dst_we1(grp_ipred_dc_fu_257_dst_we1),
- .dst_d1(grp_ipred_dc_fu_257_dst_d1),
- .w(cu_w),
- .h(cu_h),
- .cu_org_0_address0(grp_ipred_dc_fu_257_cu_org_0_address0),
- .cu_org_0_ce0(grp_ipred_dc_fu_257_cu_org_0_ce0),
- .cu_org_0_q0(cu_org0_0_q0),
- .cu_org_1_address0(grp_ipred_dc_fu_257_cu_org_1_address0),
- .cu_org_1_ce0(grp_ipred_dc_fu_257_cu_org_1_ce0),
- .cu_org_1_q0(cu_org0_1_q0),
- .resi_0_address0(grp_ipred_dc_fu_257_resi_0_address0),
- .resi_0_ce0(grp_ipred_dc_fu_257_resi_0_ce0),
- .resi_0_we0(grp_ipred_dc_fu_257_resi_0_we0),
- .resi_0_d0(grp_ipred_dc_fu_257_resi_0_d0),
- .resi_1_address0(grp_ipred_dc_fu_257_resi_1_address0),
- .resi_1_ce0(grp_ipred_dc_fu_257_resi_1_ce0),
- .resi_1_we0(grp_ipred_dc_fu_257_resi_1_we0),
- .resi_1_d0(grp_ipred_dc_fu_257_resi_1_d0)
- );
-
- ipred_plane grp_ipred_plane_fu_307(
- .ap_clk(ap_clk),
- .ap_rst(ap_rst),
- .ap_start(grp_ipred_plane_fu_307_ap_start),
- .ap_done(grp_ipred_plane_fu_307_ap_done),
- .ap_idle(grp_ipred_plane_fu_307_ap_idle),
- .ap_ready(grp_ipred_plane_fu_307_ap_ready),
- .src_le_address0(grp_ipred_plane_fu_307_src_le_address0),
- .src_le_ce0(grp_ipred_plane_fu_307_src_le_ce0),
- .src_le_q0(nb1_q0),
- .src_le_address1(grp_ipred_plane_fu_307_src_le_address1),
- .src_le_ce1(grp_ipred_plane_fu_307_src_le_ce1),
- .src_le_q1(nb1_q1),
- .dst_address0(grp_ipred_plane_fu_307_dst_address0),
- .dst_ce0(grp_ipred_plane_fu_307_dst_ce0),
- .dst_we0(grp_ipred_plane_fu_307_dst_we0),
- .dst_d0(grp_ipred_plane_fu_307_dst_d0),
- .w(cu_w),
- .h(cu_h),
- .cu_org_0_address0(grp_ipred_plane_fu_307_cu_org_0_address0),
- .cu_org_0_ce0(grp_ipred_plane_fu_307_cu_org_0_ce0),
- .cu_org_0_q0(cu_org1_0_q0),
- .cu_org_1_address0(grp_ipred_plane_fu_307_cu_org_1_address0),
- .cu_org_1_ce0(grp_ipred_plane_fu_307_cu_org_1_ce0),
- .cu_org_1_q0(cu_org1_1_q0),
- .resi_0_address0(grp_ipred_plane_fu_307_resi_0_address0),
- .resi_0_ce0(grp_ipred_plane_fu_307_resi_0_ce0),
- .resi_0_we0(grp_ipred_plane_fu_307_resi_0_we0),
- .resi_0_d0(grp_ipred_plane_fu_307_resi_0_d0),
- .resi_1_address0(grp_ipred_plane_fu_307_resi_1_address0),
- .resi_1_ce0(grp_ipred_plane_fu_307_resi_1_ce0),
- .resi_1_we0(grp_ipred_plane_fu_307_resi_1_we0),
- .resi_1_d0(grp_ipred_plane_fu_307_resi_1_d0)
- );
-
- ipred_bi grp_ipred_bi_fu_361(
- .ap_clk(ap_clk),
- .ap_rst(ap_rst),
- .ap_start(grp_ipred_bi_fu_361_ap_start),
- .ap_done(grp_ipred_bi_fu_361_ap_done),
- .ap_idle(grp_ipred_bi_fu_361_ap_idle),
- .ap_ready(grp_ipred_bi_fu_361_ap_ready),
- .src_le_address0(grp_ipred_bi_fu_361_src_le_address0),
- .src_le_ce0(grp_ipred_bi_fu_361_src_le_ce0),
- .src_le_q0(nb2_q0),
- .src_le_address1(grp_ipred_bi_fu_361_src_le_address1),
- .src_le_ce1(grp_ipred_bi_fu_361_src_le_ce1),
- .src_le_q1(nb2_q1),
- .dst_address0(grp_ipred_bi_fu_361_dst_address0),
- .dst_ce0(grp_ipred_bi_fu_361_dst_ce0),
- .dst_we0(grp_ipred_bi_fu_361_dst_we0),
- .dst_d0(grp_ipred_bi_fu_361_dst_d0),
- .w(cu_w),
- .h(cu_h),
- .cu_org_0_address0(grp_ipred_bi_fu_361_cu_org_0_address0),
- .cu_org_0_ce0(grp_ipred_bi_fu_361_cu_org_0_ce0),
- .cu_org_0_q0(cu_org2_0_q0),
- .cu_org_1_address0(grp_ipred_bi_fu_361_cu_org_1_address0),
- .cu_org_1_ce0(grp_ipred_bi_fu_361_cu_org_1_ce0),
- .cu_org_1_q0(cu_org2_1_q0),
- .resi_0_address0(grp_ipred_bi_fu_361_resi_0_address0),
- .resi_0_ce0(grp_ipred_bi_fu_361_resi_0_ce0),
- .resi_0_we0(grp_ipred_bi_fu_361_resi_0_we0),
- .resi_0_d0(grp_ipred_bi_fu_361_resi_0_d0),
- .resi_1_address0(grp_ipred_bi_fu_361_resi_1_address0),
- .resi_1_ce0(grp_ipred_bi_fu_361_resi_1_ce0),
- .resi_1_we0(grp_ipred_bi_fu_361_resi_1_we0),
- .resi_1_d0(grp_ipred_bi_fu_361_resi_1_d0)
- );
-
- ipred_vert grp_ipred_vert_fu_411(
- .ap_clk(ap_clk),
- .ap_rst(ap_rst),
- .ap_start(grp_ipred_vert_fu_411_ap_start),
- .ap_done(grp_ipred_vert_fu_411_ap_done),
- .ap_idle(grp_ipred_vert_fu_411_ap_idle),
- .ap_ready(grp_ipred_vert_fu_411_ap_ready),
- .src_up_address0(grp_ipred_vert_fu_411_src_up_address0),
- .src_up_ce0(grp_ipred_vert_fu_411_src_up_ce0),
- .src_up_q0(nb3up_q0),
- .src_up_address1(grp_ipred_vert_fu_411_src_up_address1),
- .src_up_ce1(grp_ipred_vert_fu_411_src_up_ce1),
- .src_up_q1(nb3up_q1),
- .dst_address0(grp_ipred_vert_fu_411_dst_address0),
- .dst_ce0(grp_ipred_vert_fu_411_dst_ce0),
- .dst_we0(grp_ipred_vert_fu_411_dst_we0),
- .dst_d0(grp_ipred_vert_fu_411_dst_d0),
- .w(cu_w),
- .h(cu_h),
- .resi_0_address0(grp_ipred_vert_fu_411_resi_0_address0),
- .resi_0_ce0(grp_ipred_vert_fu_411_resi_0_ce0),
- .resi_0_we0(grp_ipred_vert_fu_411_resi_0_we0),
- .resi_0_d0(grp_ipred_vert_fu_411_resi_0_d0),
- .resi_1_address0(grp_ipred_vert_fu_411_resi_1_address0),
- .resi_1_ce0(grp_ipred_vert_fu_411_resi_1_ce0),
- .resi_1_we0(grp_ipred_vert_fu_411_resi_1_we0),
- .resi_1_d0(grp_ipred_vert_fu_411_resi_1_d0),
- .cu_org3_1_address0(grp_ipred_vert_fu_411_cu_org3_1_address0),
- .cu_org3_1_ce0(grp_ipred_vert_fu_411_cu_org3_1_ce0),
- .cu_org3_1_q0(cu_org3_1_q0),
- .cu_org3_0_address0(grp_ipred_vert_fu_411_cu_org3_0_address0),
- .cu_org3_0_ce0(grp_ipred_vert_fu_411_cu_org3_0_ce0),
- .cu_org3_0_q0(cu_org3_0_q0)
- );
-
- ipred_hor grp_ipred_hor_fu_453(
- .ap_clk(ap_clk),
- .ap_rst(ap_rst),
- .ap_start(grp_ipred_hor_fu_453_ap_start),
- .ap_done(grp_ipred_hor_fu_453_ap_done),
- .ap_idle(grp_ipred_hor_fu_453_ap_idle),
- .ap_ready(grp_ipred_hor_fu_453_ap_ready),
- .src_le_address0(grp_ipred_hor_fu_453_src_le_address0),
- .src_le_ce0(grp_ipred_hor_fu_453_src_le_ce0),
- .src_le_q0(nb3le_q0),
- .dst_address0(grp_ipred_hor_fu_453_dst_address0),
- .dst_ce0(grp_ipred_hor_fu_453_dst_ce0),
- .dst_we0(grp_ipred_hor_fu_453_dst_we0),
- .dst_d0(grp_ipred_hor_fu_453_dst_d0),
- .w(cu_w),
- .h(cu_h),
- .resi_0_address0(grp_ipred_hor_fu_453_resi_0_address0),
- .resi_0_ce0(grp_ipred_hor_fu_453_resi_0_ce0),
- .resi_0_we0(grp_ipred_hor_fu_453_resi_0_we0),
- .resi_0_d0(grp_ipred_hor_fu_453_resi_0_d0),
- .resi_1_address0(grp_ipred_hor_fu_453_resi_1_address0),
- .resi_1_ce0(grp_ipred_hor_fu_453_resi_1_ce0),
- .resi_1_we0(grp_ipred_hor_fu_453_resi_1_we0),
- .resi_1_d0(grp_ipred_hor_fu_453_resi_1_d0),
- .cu_org4_1_address0(grp_ipred_hor_fu_453_cu_org4_1_address0),
- .cu_org4_1_ce0(grp_ipred_hor_fu_453_cu_org4_1_ce0),
- .cu_org4_1_q0(cu_org4_1_q0),
- .cu_org4_0_address0(grp_ipred_hor_fu_453_cu_org4_0_address0),
- .cu_org4_0_ce0(grp_ipred_hor_fu_453_cu_org4_0_ce0),
- .cu_org4_0_q0(cu_org4_0_q0)
- );
-
- ipred_ang grp_ipred_ang_fu_495(
- .ap_clk(ap_clk),
- .ap_rst(ap_rst),
- .ap_start(grp_ipred_ang_fu_495_ap_start),
- .ap_done(grp_ipred_ang_fu_495_ap_done),
- .ap_idle(grp_ipred_ang_fu_495_ap_idle),
- .ap_ready(grp_ipred_ang_fu_495_ap_ready),
- .src_le0_address0(grp_ipred_ang_fu_495_src_le0_address0),
- .src_le0_ce0(grp_ipred_ang_fu_495_src_le0_ce0),
- .src_le0_q0(nb4_q0),
- .src_le0_address1(grp_ipred_ang_fu_495_src_le0_address1),
- .src_le0_ce1(grp_ipred_ang_fu_495_src_le0_ce1),
- .src_le0_q1(nb4_q1),
- .src_le1_address0(grp_ipred_ang_fu_495_src_le1_address0),
- .src_le1_ce0(grp_ipred_ang_fu_495_src_le1_ce0),
- .src_le1_q0(nb5_q0),
- .src_le1_address1(grp_ipred_ang_fu_495_src_le1_address1),
- .src_le1_ce1(grp_ipred_ang_fu_495_src_le1_ce1),
- .src_le1_q1(nb5_q1),
- .dst_address0(grp_ipred_ang_fu_495_dst_address0),
- .dst_ce0(grp_ipred_ang_fu_495_dst_ce0),
- .dst_we0(grp_ipred_ang_fu_495_dst_we0),
- .dst_d0(grp_ipred_ang_fu_495_dst_d0),
- .w(cu_w),
- .h(cu_h),
- .ipm(ipm_ang),
- .cu_org_0_address0(grp_ipred_ang_fu_495_cu_org_0_address0),
- .cu_org_0_ce0(grp_ipred_ang_fu_495_cu_org_0_ce0),
- .cu_org_0_q0(cu_org5_0_q0),
- .cu_org_1_address0(grp_ipred_ang_fu_495_cu_org_1_address0),
- .cu_org_1_ce0(grp_ipred_ang_fu_495_cu_org_1_ce0),
- .cu_org_1_q0(cu_org5_1_q0),
- .resi_0_address0(grp_ipred_ang_fu_495_resi_0_address0),
- .resi_0_ce0(grp_ipred_ang_fu_495_resi_0_ce0),
- .resi_0_we0(grp_ipred_ang_fu_495_resi_0_we0),
- .resi_0_d0(grp_ipred_ang_fu_495_resi_0_d0),
- .resi_1_address0(grp_ipred_ang_fu_495_resi_1_address0),
- .resi_1_ce0(grp_ipred_ang_fu_495_resi_1_ce0),
- .resi_1_we0(grp_ipred_ang_fu_495_resi_1_we0),
- .resi_1_d0(grp_ipred_ang_fu_495_resi_1_d0)
- );
-
- always @ (posedge ap_clk) begin
- if (ap_rst == 1'b1) begin
- ap_CS_fsm <= ap_ST_fsm_state1;
- end else begin
- ap_CS_fsm <= ap_NS_fsm;
- end
- end
-
- always @ (posedge ap_clk) begin
- if (ap_rst == 1'b1) begin
- grp_ipred_ang_fu_495_ap_start_reg <= 1'b0;
- end else begin
- if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
- grp_ipred_ang_fu_495_ap_start_reg <= 1'b1;
- end else if ((grp_ipred_ang_fu_495_ap_ready == 1'b1)) begin
- grp_ipred_ang_fu_495_ap_start_reg <= 1'b0;
- end
- end
- end
-
- always @ (posedge ap_clk) begin
- if (ap_rst == 1'b1) begin
- grp_ipred_bi_fu_361_ap_start_reg <= 1'b0;
- end else begin
- if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
- grp_ipred_bi_fu_361_ap_start_reg <= 1'b1;
- end else if ((grp_ipred_bi_fu_361_ap_ready == 1'b1)) begin
- grp_ipred_bi_fu_361_ap_start_reg <= 1'b0;
- end
- end
- end
-
- always @ (posedge ap_clk) begin
- if (ap_rst == 1'b1) begin
- grp_ipred_dc_fu_257_ap_start_reg <= 1'b0;
- end else begin
- if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
- grp_ipred_dc_fu_257_ap_start_reg <= 1'b1;
- end else if ((grp_ipred_dc_fu_257_ap_ready == 1'b1)) begin
- grp_ipred_dc_fu_257_ap_start_reg <= 1'b0;
- end
- end
- end
-
- always @ (posedge ap_clk) begin
- if (ap_rst == 1'b1) begin
- grp_ipred_hor_fu_453_ap_start_reg <= 1'b0;
- end else begin
- if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
- grp_ipred_hor_fu_453_ap_start_reg <= 1'b1;
- end else if ((grp_ipred_hor_fu_453_ap_ready == 1'b1)) begin
- grp_ipred_hor_fu_453_ap_start_reg <= 1'b0;
- end
- end
- end
-
- always @ (posedge ap_clk) begin
- if (ap_rst == 1'b1) begin
- grp_ipred_plane_fu_307_ap_start_reg <= 1'b0;
- end else begin
- if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
- grp_ipred_plane_fu_307_ap_start_reg <= 1'b1;
- end else if ((grp_ipred_plane_fu_307_ap_ready == 1'b1)) begin
- grp_ipred_plane_fu_307_ap_start_reg <= 1'b0;
- end
- end
- end
-
- always @ (posedge ap_clk) begin
- if (ap_rst == 1'b1) begin
- grp_ipred_vert_fu_411_ap_start_reg <= 1'b0;
- end else begin
- if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
- grp_ipred_vert_fu_411_ap_start_reg <= 1'b1;
- end else if ((grp_ipred_vert_fu_411_ap_ready == 1'b1)) begin
- grp_ipred_vert_fu_411_ap_start_reg <= 1'b0;
- end
- end
- end
-
- always @ (posedge ap_clk) begin
- if (((icmp_ln2106_fu_600_p2 == 1'd0) & (ap_phi_mux_i_0_phi_fu_250_p4 == 3'd1) & (1'b1 == ap_CS_fsm_state3))) begin
- cost14_0_fu_184 <= 24'd0;
- end else if (((1'b0 == ap_block_state2_on_subcall_done) & (1'b1 == ap_CS_fsm_state2))) begin
- cost14_0_fu_184 <= cost_1_read;
- end
- end
-
- always @ (posedge ap_clk) begin
- if (((icmp_ln2106_fu_600_p2 == 1'd0) & (ap_phi_mux_i_0_phi_fu_250_p4 == 3'd2) & (1'b1 == ap_CS_fsm_state3))) begin
- cost15_0_fu_180 <= 24'd0;
- end else if (((1'b0 == ap_block_state2_on_subcall_done) & (1'b1 == ap_CS_fsm_state2))) begin
- cost15_0_fu_180 <= cost_2_read;
- end
- end
-
- always @ (posedge ap_clk) begin
- if (((icmp_ln2106_fu_600_p2 == 1'd0) & (ap_phi_mux_i_0_phi_fu_250_p4 == 3'd3) & (1'b1 == ap_CS_fsm_state3))) begin
- cost16_0_fu_176 <= 24'd0;
- end else if (((1'b0 == ap_block_state2_on_subcall_done) & (1'b1 == ap_CS_fsm_state2))) begin
- cost16_0_fu_176 <= cost_3_read;
- end
- end
-
- always @ (posedge ap_clk) begin
- if (((icmp_ln2106_fu_600_p2 == 1'd0) & (ap_phi_mux_i_0_phi_fu_250_p4 == 3'd4) & (1'b1 == ap_CS_fsm_state3))) begin
- cost17_0_fu_172 <= 24'd0;
- end else if (((1'b0 == ap_block_state2_on_subcall_done) & (1'b1 == ap_CS_fsm_state2))) begin
- cost17_0_fu_172 <= cost_4_read;
- end
- end
-
- always @ (posedge ap_clk) begin
- if ((~(ap_phi_mux_i_0_phi_fu_250_p4 == 3'd4) & ~(ap_phi_mux_i_0_phi_fu_250_p4 == 3'd3) & ~(ap_phi_mux_i_0_phi_fu_250_p4 == 3'd2) & ~(ap_phi_mux_i_0_phi_fu_250_p4 == 3'd1) & ~(ap_phi_mux_i_0_phi_fu_250_p4 == 3'd0) & (icmp_ln2106_fu_600_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state3))) begin
- cost18_0_fu_168 <= 24'd0;
- end else if (((1'b0 == ap_block_state2_on_subcall_done) & (1'b1 == ap_CS_fsm_state2))) begin
- cost18_0_fu_168 <= cost_5_read;
- end
- end
-
- always @ (posedge ap_clk) begin
- if (((icmp_ln2106_fu_600_p2 == 1'd0) & (ap_phi_mux_i_0_phi_fu_250_p4 == 3'd0) & (1'b1 == ap_CS_fsm_state3))) begin
- cost_0_fu_188 <= 24'd0;
- end else if (((1'b0 == ap_block_state2_on_subcall_done) & (1'b1 == ap_CS_fsm_state2))) begin
- cost_0_fu_188 <= cost_0_read;
- end
- end
-
- always @ (posedge ap_clk) begin
- if (((icmp_ln2106_fu_600_p2 == 1'd0) & (1'b1 == ap_CS_fsm_state3))) begin
- i_0_reg_246 <= i_fu_606_p2;
- end else if (((1'b0 == ap_block_state2_on_subcall_done) & (1'b1 == ap_CS_fsm_state2))) begin
- i_0_reg_246 <= 3'd0;
- end
- end
-
- always @ (*) begin
- if ((((icmp_ln2106_fu_600_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state3)) | ((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1)))) begin
- ap_done = 1'b1;
- end else begin
- ap_done = 1'b0;
- end
- end
-
- always @ (*) begin
- if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
- ap_idle = 1'b1;
- end else begin
- ap_idle = 1'b0;
- end
- end
-
- always @ (*) begin
- if (((icmp_ln2106_fu_600_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state3))) begin
- ap_ready = 1'b1;
- end else begin
- ap_ready = 1'b0;
- end
- end
-
- always @ (*) begin
- case (ap_CS_fsm)
- ap_ST_fsm_state1 : begin
- if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
- ap_NS_fsm = ap_ST_fsm_state2;
- end else begin
- ap_NS_fsm = ap_ST_fsm_state1;
- end
- end
- ap_ST_fsm_state2 : begin
- if (((1'b0 == ap_block_state2_on_subcall_done) & (1'b1 == ap_CS_fsm_state2))) begin
- ap_NS_fsm = ap_ST_fsm_state3;
- end else begin
- ap_NS_fsm = ap_ST_fsm_state2;
- end
- end
- ap_ST_fsm_state3 : begin
- if (((icmp_ln2106_fu_600_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state3))) begin
- ap_NS_fsm = ap_ST_fsm_state1;
- end else begin
- ap_NS_fsm = ap_ST_fsm_state3;
- end
- end
- default : begin
- ap_NS_fsm = 'bx;
- end
- endcase
- end
-
- assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
-
- assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];
-
- assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2];
-
- always @ (*) begin
- ap_block_state2_on_subcall_done = ((grp_ipred_ang_fu_495_ap_done == 1'b0) | (grp_ipred_hor_fu_453_ap_done == 1'b0) | (grp_ipred_vert_fu_411_ap_done == 1'b0) | (grp_ipred_bi_fu_361_ap_done == 1'b0) | (grp_ipred_plane_fu_307_ap_done == 1'b0) | (grp_ipred_dc_fu_257_ap_done == 1'b0));
- end
-
- assign ap_phi_mux_i_0_phi_fu_250_p4 = i_0_reg_246;
-
- assign ap_return_0 = cost_0_fu_188;
-
- assign ap_return_1 = cost14_0_fu_184;
-
- assign ap_return_2 = cost15_0_fu_180;
-
- assign ap_return_3 = cost16_0_fu_176;
-
- assign ap_return_4 = cost17_0_fu_172;
-
- assign ap_return_5 = cost18_0_fu_168;
-
- assign cu_org0_0_address0 = grp_ipred_dc_fu_257_cu_org_0_address0;
-
- assign cu_org0_0_ce0 = grp_ipred_dc_fu_257_cu_org_0_ce0;
-
- assign cu_org0_1_address0 = grp_ipred_dc_fu_257_cu_org_1_address0;
-
- assign cu_org0_1_ce0 = grp_ipred_dc_fu_257_cu_org_1_ce0;
-
- assign cu_org1_0_address0 = grp_ipred_plane_fu_307_cu_org_0_address0;
-
- assign cu_org1_0_ce0 = grp_ipred_plane_fu_307_cu_org_0_ce0;
-
- assign cu_org1_1_address0 = grp_ipred_plane_fu_307_cu_org_1_address0;
-
- assign cu_org1_1_ce0 = grp_ipred_plane_fu_307_cu_org_1_ce0;
-
- assign cu_org2_0_address0 = grp_ipred_bi_fu_361_cu_org_0_address0;
-
- assign cu_org2_0_ce0 = grp_ipred_bi_fu_361_cu_org_0_ce0;
-
- assign cu_org2_1_address0 = grp_ipred_bi_fu_361_cu_org_1_address0;
-
- assign cu_org2_1_ce0 = grp_ipred_bi_fu_361_cu_org_1_ce0;
-
- assign cu_org3_0_address0 = grp_ipred_vert_fu_411_cu_org3_0_address0;
-
- assign cu_org3_0_ce0 = grp_ipred_vert_fu_411_cu_org3_0_ce0;
-
- assign cu_org3_1_address0 = grp_ipred_vert_fu_411_cu_org3_1_address0;
-
- assign cu_org3_1_ce0 = grp_ipred_vert_fu_411_cu_org3_1_ce0;
-
- assign cu_org4_0_address0 = grp_ipred_hor_fu_453_cu_org4_0_address0;
-
- assign cu_org4_0_ce0 = grp_ipred_hor_fu_453_cu_org4_0_ce0;
-
- assign cu_org4_1_address0 = grp_ipred_hor_fu_453_cu_org4_1_address0;
-
- assign cu_org4_1_ce0 = grp_ipred_hor_fu_453_cu_org4_1_ce0;
-
- assign cu_org5_0_address0 = grp_ipred_ang_fu_495_cu_org_0_address0;
-
- assign cu_org5_0_ce0 = grp_ipred_ang_fu_495_cu_org_0_ce0;
-
- assign cu_org5_1_address0 = grp_ipred_ang_fu_495_cu_org_1_address0;
-
- assign cu_org5_1_ce0 = grp_ipred_ang_fu_495_cu_org_1_ce0;
-
- assign dst0_address0 = grp_ipred_dc_fu_257_dst_address0;
-
- assign dst0_address1 = grp_ipred_dc_fu_257_dst_address1;
-
- assign dst0_ce0 = grp_ipred_dc_fu_257_dst_ce0;
-
- assign dst0_ce1 = grp_ipred_dc_fu_257_dst_ce1;
-
- assign dst0_d0 = grp_ipred_dc_fu_257_dst_d0;
-
- assign dst0_d1 = grp_ipred_dc_fu_257_dst_d1;
-
- assign dst0_we0 = grp_ipred_dc_fu_257_dst_we0;
-
- assign dst0_we1 = grp_ipred_dc_fu_257_dst_we1;
-
- assign dst1_address0 = grp_ipred_plane_fu_307_dst_address0;
-
- assign dst1_ce0 = grp_ipred_plane_fu_307_dst_ce0;
-
- assign dst1_d0 = grp_ipred_plane_fu_307_dst_d0;
-
- assign dst1_we0 = grp_ipred_plane_fu_307_dst_we0;
-
- assign dst2_address0 = grp_ipred_bi_fu_361_dst_address0;
-
- assign dst2_ce0 = grp_ipred_bi_fu_361_dst_ce0;
-
- assign dst2_d0 = grp_ipred_bi_fu_361_dst_d0;
-
- assign dst2_we0 = grp_ipred_bi_fu_361_dst_we0;
-
- assign dst3_address0 = grp_ipred_vert_fu_411_dst_address0;
-
- assign dst3_ce0 = grp_ipred_vert_fu_411_dst_ce0;
-
- assign dst3_d0 = grp_ipred_vert_fu_411_dst_d0;
-
- assign dst3_we0 = grp_ipred_vert_fu_411_dst_we0;
-
- assign dst4_address0 = grp_ipred_hor_fu_453_dst_address0;
-
- assign dst4_ce0 = grp_ipred_hor_fu_453_dst_ce0;
-
- assign dst4_d0 = grp_ipred_hor_fu_453_dst_d0;
-
- assign dst4_we0 = grp_ipred_hor_fu_453_dst_we0;
-
- assign dst5_address0 = grp_ipred_ang_fu_495_dst_address0;
-
- assign dst5_ce0 = grp_ipred_ang_fu_495_dst_ce0;
-
- assign dst5_d0 = grp_ipred_ang_fu_495_dst_d0;
-
- assign dst5_we0 = grp_ipred_ang_fu_495_dst_we0;
-
- assign grp_ipred_ang_fu_495_ap_start = grp_ipred_ang_fu_495_ap_start_reg;
-
- assign grp_ipred_bi_fu_361_ap_start = grp_ipred_bi_fu_361_ap_start_reg;
-
- assign grp_ipred_dc_fu_257_ap_start = grp_ipred_dc_fu_257_ap_start_reg;
-
- assign grp_ipred_hor_fu_453_ap_start = grp_ipred_hor_fu_453_ap_start_reg;
-
- assign grp_ipred_plane_fu_307_ap_start = grp_ipred_plane_fu_307_ap_start_reg;
-
- assign grp_ipred_vert_fu_411_ap_start = grp_ipred_vert_fu_411_ap_start_reg;
-
- assign i_fu_606_p2 = (i_0_reg_246 + 3'd1);
-
- assign icmp_ln2106_fu_600_p2 = ((i_0_reg_246 == 3'd6) ? 1'b1 : 1'b0);
-
- assign nb0_0_address0 = grp_ipred_dc_fu_257_src_up_address0;
-
- assign nb0_0_ce0 = grp_ipred_dc_fu_257_src_up_ce0;
-
- assign nb0_1_address0 = grp_ipred_dc_fu_257_src_up2_address0;
-
- assign nb0_1_ce0 = grp_ipred_dc_fu_257_src_up2_ce0;
-
- assign nb1_address0 = grp_ipred_plane_fu_307_src_le_address0;
-
- assign nb1_address1 = grp_ipred_plane_fu_307_src_le_address1;
-
- assign nb1_ce0 = grp_ipred_plane_fu_307_src_le_ce0;
-
- assign nb1_ce1 = grp_ipred_plane_fu_307_src_le_ce1;
-
- assign nb2_address0 = grp_ipred_bi_fu_361_src_le_address0;
-
- assign nb2_address1 = grp_ipred_bi_fu_361_src_le_address1;
-
- assign nb2_ce0 = grp_ipred_bi_fu_361_src_le_ce0;
-
- assign nb2_ce1 = grp_ipred_bi_fu_361_src_le_ce1;
-
- assign nb3le_address0 = grp_ipred_hor_fu_453_src_le_address0;
-
- assign nb3le_ce0 = grp_ipred_hor_fu_453_src_le_ce0;
-
- assign nb3up_address0 = grp_ipred_vert_fu_411_src_up_address0;
-
- assign nb3up_address1 = grp_ipred_vert_fu_411_src_up_address1;
-
- assign nb3up_ce0 = grp_ipred_vert_fu_411_src_up_ce0;
-
- assign nb3up_ce1 = grp_ipred_vert_fu_411_src_up_ce1;
-
- assign nb4_address0 = grp_ipred_ang_fu_495_src_le0_address0;
-
- assign nb4_address1 = grp_ipred_ang_fu_495_src_le0_address1;
-
- assign nb4_ce0 = grp_ipred_ang_fu_495_src_le0_ce0;
-
- assign nb4_ce1 = grp_ipred_ang_fu_495_src_le0_ce1;
-
- assign nb5_address0 = grp_ipred_ang_fu_495_src_le1_address0;
-
- assign nb5_address1 = grp_ipred_ang_fu_495_src_le1_address1;
-
- assign nb5_ce0 = grp_ipred_ang_fu_495_src_le1_ce0;
-
- assign nb5_ce1 = grp_ipred_ang_fu_495_src_le1_ce1;
-
- assign resi0_0_address0 = grp_ipred_dc_fu_257_resi_0_address0;
-
- assign resi0_0_ce0 = grp_ipred_dc_fu_257_resi_0_ce0;
-
- assign resi0_0_d0 = grp_ipred_dc_fu_257_resi_0_d0;
-
- assign resi0_0_we0 = grp_ipred_dc_fu_257_resi_0_we0;
-
- assign resi0_1_address0 = grp_ipred_dc_fu_257_resi_1_address0;
-
- assign resi0_1_ce0 = grp_ipred_dc_fu_257_resi_1_ce0;
-
- assign resi0_1_d0 = grp_ipred_dc_fu_257_resi_1_d0;
-
- assign resi0_1_we0 = grp_ipred_dc_fu_257_resi_1_we0;
-
- assign resi1_0_address0 = grp_ipred_plane_fu_307_resi_0_address0;
-
- assign resi1_0_ce0 = grp_ipred_plane_fu_307_resi_0_ce0;
-
- assign resi1_0_d0 = grp_ipred_plane_fu_307_resi_0_d0;
-
- assign resi1_0_we0 = grp_ipred_plane_fu_307_resi_0_we0;
-
- assign resi1_1_address0 = grp_ipred_plane_fu_307_resi_1_address0;
-
- assign resi1_1_ce0 = grp_ipred_plane_fu_307_resi_1_ce0;
-
- assign resi1_1_d0 = grp_ipred_plane_fu_307_resi_1_d0;
-
- assign resi1_1_we0 = grp_ipred_plane_fu_307_resi_1_we0;
-
- assign resi2_0_address0 = grp_ipred_bi_fu_361_resi_0_address0;
-
- assign resi2_0_ce0 = grp_ipred_bi_fu_361_resi_0_ce0;
-
- assign resi2_0_d0 = grp_ipred_bi_fu_361_resi_0_d0;
-
- assign resi2_0_we0 = grp_ipred_bi_fu_361_resi_0_we0;
-
- assign resi2_1_address0 = grp_ipred_bi_fu_361_resi_1_address0;
-
- assign resi2_1_ce0 = grp_ipred_bi_fu_361_resi_1_ce0;
-
- assign resi2_1_d0 = grp_ipred_bi_fu_361_resi_1_d0;
-
- assign resi2_1_we0 = grp_ipred_bi_fu_361_resi_1_we0;
-
- assign resi3_0_address0 = grp_ipred_vert_fu_411_resi_0_address0;
-
- assign resi3_0_ce0 = grp_ipred_vert_fu_411_resi_0_ce0;
-
- assign resi3_0_d0 = grp_ipred_vert_fu_411_resi_0_d0;
-
- assign resi3_0_we0 = grp_ipred_vert_fu_411_resi_0_we0;
-
- assign resi3_1_address0 = grp_ipred_vert_fu_411_resi_1_address0;
-
- assign resi3_1_ce0 = grp_ipred_vert_fu_411_resi_1_ce0;
-
- assign resi3_1_d0 = grp_ipred_vert_fu_411_resi_1_d0;
-
- assign resi3_1_we0 = grp_ipred_vert_fu_411_resi_1_we0;
-
- assign resi4_0_address0 = grp_ipred_hor_fu_453_resi_0_address0;
-
- assign resi4_0_ce0 = grp_ipred_hor_fu_453_resi_0_ce0;
-
- assign resi4_0_d0 = grp_ipred_hor_fu_453_resi_0_d0;
-
- assign resi4_0_we0 = grp_ipred_hor_fu_453_resi_0_we0;
-
- assign resi4_1_address0 = grp_ipred_hor_fu_453_resi_1_address0;
-
- assign resi4_1_ce0 = grp_ipred_hor_fu_453_resi_1_ce0;
-
- assign resi4_1_d0 = grp_ipred_hor_fu_453_resi_1_d0;
-
- assign resi4_1_we0 = grp_ipred_hor_fu_453_resi_1_we0;
-
- assign resi5_0_address0 = grp_ipred_ang_fu_495_resi_0_address0;
-
- assign resi5_0_ce0 = grp_ipred_ang_fu_495_resi_0_ce0;
-
- assign resi5_0_d0 = grp_ipred_ang_fu_495_resi_0_d0;
-
- assign resi5_0_we0 = grp_ipred_ang_fu_495_resi_0_we0;
-
- assign resi5_1_address0 = grp_ipred_ang_fu_495_resi_1_address0;
-
- assign resi5_1_ce0 = grp_ipred_ang_fu_495_resi_1_ce0;
-
- assign resi5_1_d0 = grp_ipred_ang_fu_495_resi_1_d0;
-
- assign resi5_1_we0 = grp_ipred_ang_fu_495_resi_1_we0;
-
- endmodule //select_ipm
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