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- //
- // Generated by NVIDIA NVVM Compiler
- //
- // Compiler Build ID: CL-26907403
- // Cuda compilation tools, release 10.1, V10.1.243
- // Based on LLVM 3.4svn
- //
-
- .version 6.4
- .target sm_60
- .address_size 64
-
- // .globl Fused_Mul_Maximum_fusion_3046152682408121495_kernel0
-
- .visible .entry Fused_Mul_Maximum_fusion_3046152682408121495_kernel0(
- .param .u64 Fused_Mul_Maximum_fusion_3046152682408121495_kernel0_param_0,
- .param .u64 Fused_Mul_Maximum_fusion_3046152682408121495_kernel0_param_1,
- .param .u64 Fused_Mul_Maximum_fusion_3046152682408121495_kernel0_param_2
- )
- {
- .reg .pred %p<4>;
- .reg .f32 %f<33>;
- .reg .b32 %r<6>;
- .reg .b64 %rd<15>;
-
-
- ld.param.u64 %rd4, [Fused_Mul_Maximum_fusion_3046152682408121495_kernel0_param_0];
- ld.param.u64 %rd5, [Fused_Mul_Maximum_fusion_3046152682408121495_kernel0_param_1];
- ld.param.u64 %rd6, [Fused_Mul_Maximum_fusion_3046152682408121495_kernel0_param_2];
- cvta.to.global.u64 %rd1, %rd5;
- cvta.to.global.u64 %rd2, %rd6;
- cvta.to.global.u64 %rd3, %rd4;
- mov.u32 %r1, %tid.x;
- setp.gt.s32 %p1, %r1, 743;
- @%p1 bra BB0_5;
-
- mov.u32 %r2, %ctaid.x;
- setp.lt.s32 %p2, %r2, 165;
- @%p2 bra BB0_4;
- bra.uni BB0_2;
-
- BB0_4:
- shl.b32 %r4, %r1, 2;
- mad.lo.s32 %r5, %r2, 2976, %r4;
- mul.wide.s32 %rd11, %r5, 4;
- add.s64 %rd12, %rd3, %rd11;
- ld.global.nc.v4.f32 {%f17, %f18, %f19, %f20}, [%rd12];
- add.s64 %rd13, %rd2, %rd11;
- mul.f32 %f25, %f20, 0f3E4CCCCD;
- max.f32 %f26, %f25, %f20;
- mul.f32 %f27, %f19, 0f3E4CCCCD;
- max.f32 %f28, %f27, %f19;
- mul.f32 %f29, %f18, 0f3E4CCCCD;
- max.f32 %f30, %f29, %f18;
- mul.f32 %f31, %f17, 0f3E4CCCCD;
- max.f32 %f32, %f31, %f17;
- st.global.v4.f32 [%rd13], {%f32, %f30, %f28, %f26};
- add.s64 %rd14, %rd1, %rd11;
- st.global.v4.f32 [%rd14], {%f31, %f29, %f27, %f25};
- bra.uni BB0_5;
-
- BB0_2:
- setp.gt.s32 %p3, %r1, 247;
- @%p3 bra BB0_5;
-
- shl.b32 %r3, %r1, 2;
- mul.wide.s32 %rd7, %r3, 4;
- add.s64 %rd8, %rd3, %rd7;
- ld.global.nc.v4.f32 {%f1, %f2, %f3, %f4}, [%rd8+1964160];
- add.s64 %rd9, %rd2, %rd7;
- mul.f32 %f9, %f4, 0f3E4CCCCD;
- max.f32 %f10, %f9, %f4;
- mul.f32 %f11, %f3, 0f3E4CCCCD;
- max.f32 %f12, %f11, %f3;
- mul.f32 %f13, %f2, 0f3E4CCCCD;
- max.f32 %f14, %f13, %f2;
- mul.f32 %f15, %f1, 0f3E4CCCCD;
- max.f32 %f16, %f15, %f1;
- st.global.v4.f32 [%rd9+1964160], {%f16, %f14, %f12, %f10};
- add.s64 %rd10, %rd1, %rd7;
- st.global.v4.f32 [%rd10+1964160], {%f15, %f13, %f11, %f9};
-
- BB0_5:
- ret;
- }
-
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